Embodiments of the present invention relate to the field of semiconductor devices. In particular, embodiments of the present invention relate to the protection of semiconductor devices against electrical over-stress (EOS) and electrostatic discharge (ESD).
Integrated circuits (ICs) are sensitive to electrostatic discharge (ESD) and electrical over-stress (EOS). This is particularly true for ICs that are fabricated using metal-oxide semiconductor (MOS) technology. The thin oxide films used to insulate the gates of MOS transistors have relatively low breakdown voltages, and the individual gates are typically designed to have low capacitance.
In order to protect integrated circuits from ESD damage, protection circuits are frequently integrated on the chip. These protection circuits are usually adjacent to bonding pads where input and output signal leads are attached. Protection is typically provided by switches (e.g. diodes) that open to provide a shunt path to divert the energy of a static discharge into the IC, and/or capacitors that can absorb a static charge and reduce the voltage seen by the rest of the IC.
In the past, silicon p-n junction diodes have been used to clamp spikes at the inherent forward voltage drop of 0.6 to 0.7 volts. However, as smaller transistors are developed and power supply voltages are reduced, diodes that can clamp at a smaller forward voltage are required.
Schottky diodes can be used to provide clamping at forward voltages that are smaller than those of the silicon diode; however, the fabrication of Schottky diodes can increase the complexity of IC processing by requiring an additional metal deposition.
Another difficulty associated with the use of diodes is that in order to protect a signal line from both positive and negative voltages, a pair of diodes must be used, which can create an equivalent silicon controlled rectifier (SCR) structure in bipolar and complementary metal-oxide semiconductor (CMOS) technology that is susceptible to latch-up.
Conventional ESD protection devices in ICs require a part of the available wafer area in order to provide protection. The circuit elements that must be protected from EOS/ESD energy surges are shrinking in size, whereas the energy surges that must be protected against are not.
Accordingly, an ESD protection device for integrated circuits that requires no additional wafer area and avoids many of the problems associated with diode protection schemes is described herein.
More specifically, in an embodiment of the present invention, an enhancement mode junction field effect transistor (JFET) is fabricated in a complementary well that is located beneath an interface bonding pad associated with a signal line that is to be protected. The gate and drain of the enhancement mode JFET are connected to the bonding pad, whereas the source of the JFET is coupled to the IC substrate and to a source contact on the complementary well.
In another embodiment of the present invention, the gate of the enhancement mode JFET is fabricated concurrently with other devices in the integrated circuit, thus eliminating the need for additional process steps. Thus, the overhead associated with the addition of the JFET structure is limited to mask features. Since the threshold voltage (Vth) of the JFET can be adjusted through mask features, different bonding pads on the same chip can be provided with protection devices having different threshold voltages, and the magnitude of the threshold voltage for the JFET can be set below 0.5 volts. Thus, an n-channel JFET may have a threshold voltage less than +0.5 volts, and a p-channel JFET may have a threshold voltage above xe2x88x920.5 volts.
In a further embodiment, the gate of the enhancement mode JFET is fabricated as a gate grid structure, having multiple channels. The gate grid structure allows the total channel cross-section to be varied independently from the threshold voltage, and can be easily adjusted to match the size of the bonding pad.